The conventional way of supporting and protecting individual very large-scale integrated circuit chips and gate array chips consists of mounting such chips in a single chip package or in a multi-chip hybrid circuit package. The packages are then mounted on printed wiring boards and associated with a plurality of other such printed wiring boards. The printed wiring boards are protected and enclosed in a comparatively large enclosure. Volume efficiency of such electronic packaging is very low because there is a great deal of printed wiring board, enclosure and package for each chip. Similarly, the weight is high for the same reasons. Circuit performance is impaired by long signal lines with concomitant undesirable impedance, crosstalk, excessive capacitance, uneven power forms, voltage drops and other electrical problems. In order to reduce the very great number of interconnections external to the integrated circuit in conventional packaging, in accordance with this invention it is practical to interconnect circuit elements at the wafer level, providing element yields are sufficiently high to permit this. The net number of external connections from a complex wafer can be vastly lower than if the elements are separated and individually packaged as chips. This however, then requires that wafers be interconnected directly, rather than as individual chips in packages. Thus, there is need for providing an interconnection method which permits the dense packaging of high density, integrated circuit wafers, together with permitting connections to the wafers and cooling of the wafers while the wafers are well protected from hostile environment.